In semiconductor device manufacturing, 3D monolithic designs comprise stacked layers of devices (e.g., field-effect transistor (FET) devices) that are sequentially processed to reduce a device footprint. For example, a FET-over-FET integration scheme is one form of 3D monolithic integration in which p-type and n-type FET devices are separately formed on different device layers of a 3D monolithic semiconductor IC device. The separation of p-type and n-type FET devices provides certain advantages such as the ability to use more optimal or compatible semiconductor materials (e.g., germanium, silicon-germanium, silicon, group III-V compound semiconductor materials, etc.) on different layers to enhance or otherwise optimize device performance.
Monolithic 3D semiconductor IC devices are fabricated using one of various conventional methods. For example, one conventional process involves fabricating a lower device layer with FET devices, and then bonding a semiconductor substrate (e.g., pristine silicon layer or silicon-on-insulator (SOI) substrate) to the lower device layer, followed by upper layer device processing to fabricate FET devices on the semiconductor substrate and connections to the lower device layer. This conventional scheme is problematic as it requires fine lithographic alignment of the devices and connections between the upper and lower device layers.